# InfoCoBuild

## Digital System Design

Digital System Design. Instructor: Prof. Neeraj Goel, Department of Computer Science and Engineering, IIT Ropar. Digital system design course focuses on designing digital systems from scratch. The course focuses on designing combinational and sequential building blocks, using these building blocks to design bigger digital systems. During this course we also learn how to use Verilog to design/model a digital system. (from nptel.ac.in)

 Digital System Design

 Lecture 01 - Introduction Lecture 02 - Analog vs Digital Lecture 03 - Binary Number System, Part 1 Lecture 04 - Binary Number System, Part 2 Lecture 05 - Negative Number Representation, Part 1 Lecture 06 - Negative Number Representation, Part 2 Lecture 07 - Other Number Systems Lecture 08 - Floating Point Numbers, Part 1 Lecture 09 - Floating Point Numbers, Part 2 Lecture 10 - Floating Point Numbers, Part 3 Lecture 11 - Floating Point Numbers, Part 4 Lecture 12 - Floating Point Numbers, Part 5 Lecture 13 - Boolean Functions Lecture 14 - Boolean Algebra Lecture 15 - SOP and POS Representation Lecture 16 - Algebraic Simplifications Lecture 17 - Canonical Form Lecture 18 - Boolean Minimization using Karnaugh Maps Lecture 19 - More Logic Gates Lecture 20 - Hardware Description Language: Verilog Lecture 21 - Verilog Simulation Demo Lecture 22 - Karnaugh Maps Lecture 23 - Quine-McCluskey Method Lecture 24 - Area Delay Model Lecture 25 - Multi-Level Logic Lecture 26 - Multiplexer Lecture 27 - Four Stage Logic Lecture 28 - Decoders, Part 1 Lecture 29 - Decoders, Part 2 Lecture 30 - Encoders Lecture 31 - Programmable Hardware Lecture 32 - Ripple Carry Adder Lecture 33 - Carry Look Ahead Adder Lecture 34 - Modeling BUS in Verilog Lecture 35 - Fast Adder: Carry Select Adder Lecture 36 - Multiple Operand Adder Lecture 37 - Multiplication Lecture 38 - Iterative Circuits, Part 1 Lecture 39 - Iterative Circuits, Part 2 Lecture 40 - Introduction to Sequential Circuits Lecture 41 - Latches Lecture 42 - D-Flip-Flops Lecture 43 - More Flip-Flops Lecture 44 - Counters Lecture 45 - Verilog Behavior Model, Part 1 Lecture 46 - Verilog Behavior Model, Part 2 Lecture 47 - Registers, Part 1 Lecture 48 - Registers, Part 2 Lecture 49 - Memory Lecture 50 - Sequential Circuit Analysis Lecture 51 - Derivation State Graph Lecture 52 - Sequence Detector: Example 1 Lecture 53 - Sequence Detector: Example 2 Lecture 54 - State Machine Reduction Lecture 55 - State Encoding Lecture 56 - Multicycle Adder Design Lecture 57 - Pipelined Adder Design Lecture 58 - Multiplication Design Lecture 59 - Division Hardware Design Lecture 60 - Interacting State Machines Lecture 61 - Register Transfer Level Design Lecture 62 - GCD Computer at RTL Level Lecture 63 - RTL Design: Bubble Sort Lecture 64 - RTL Design: Traffic Light Controller Lecture 65 - FPGA (Field Programmable Gate Array) Lecture 66 - Xilinx CLB Lecture 67 - FPGA Design Flow Lecture 68 - FPGA Design Demo

 References Digital System Design Instructor: Prof. Neeraj Goel, Department of Computer Science and Engineering, IIT Ropar. This course focuses on designing combinational and sequential building blocks, using these building blocks to design bigger digital systems.