InfoCoBuild

ECE 18-447: Introduction to Computer Architecture

ECE 18-447: Introduction to Computer Architecture (Spring 2014, Carnegie Mellon Univ.). Instructor: Professor Onur Mutlu. Computer architecture is the science and art of selecting and interconnecting hardware components and designing the hardware/software interface to create a computer that meets functional, performance, energy consumption, cost, and other specific goals. This course introduces the basic hardware structure of a modern programmable computer, including the basic laws underlying performance evaluation. We will learn, for example, how to design the control and data path hardware for a ARM-like processor, how to make machine instructions execute simultaneously through pipelining and simple superscalar execution, and how to design fast memory and storage systems. The principles presented in the lecture are reinforced in the laboratory through the design and simulation of a register transfer level (RTL) implementation of a MIPS-like pipelined processor in Verilog. In addition, we will develop a cycle-accurate simulator of this processor in C, and we will use this simulator to explore processor design options. (from ece.cmu.edu)

Lecture 06 - Multi-Cycle and Microprogrammed Microarchitectures


Go to the Course Home or watch other lectures:

Lecture 01 - Introduction and Basics
Lecture 02 - Fundamental Concepts and ISA
Lecture 03 - ISA Tradeoffs
Lecture 04 - ISA Tradeoffs (cont.)
Lecture 05 - Single-Cycle and Multi-Cycle Microarchitectures
Lecture 06 - Multi-Cycle and Microprogrammed Microarchitectures
Lecture 07 - Pipelining
Lecture 08 - Data and Control Dependence
Lecture 09 - Branch Handling and Branch Prediction
Lecture 10 - Branch Handling and Branch Prediction II
Lecture 11 - Precise Exceptions
Lecture 12 - Virtual Memory I
Lecture 13 - Virtual Memory II
Lecture 14 - Out-of-order Execution
Lecture 15 - Load/Store Handling and Data Flow
Lecture 16 - SIMD Processing (Vector and Array Processors)
Lecture 17 - GPUs, VLIW, Systolic Arrays
Lecture 18 - Exam 1 Review
Lecture 19 - Memory Hierarchy and Caches
Lecture 20 - Better Caching
Lecture 21 - Advanced Caching and Memory-Level Parallelism
Lecture 22 - Main Memory
Lecture 23 - DRAM and RowClone, TL-DRAM
Lecture 24 - Memory Scheduling
Lecture 25 - Main Memory Wrap-Up
Lecture 26 - Runahead Execution
Lecture 27 - Prefetching
Lecture 28 - Multiprocessors
Lecture 29 - Consistency and Coherence
Lecture 30 - Performance Predictability, Cache Compression
Lecture 31 - Interconnection Networks
Lecture 32 - Asymmetric Multi-Core
Lecture 33 - Emerging Memory Technologies