Computer Architecture

Computer Architecture. Instructor: Prof. Madhu Mutyam, Department of Computer Science and Engineering, IIT Madras. Computer architecture course deals with instruction set architecture, microarchitecture and efficient implementation of microarchitecture. Understanding the computer architecture concepts is essential for students interested in hardware, processor design, compilers, and operating systems.

In the last four decades, the number of transistors in a chip has increased from few thousands to few billions. In order to utilize the available transistors in a chip to improve computational power, various micro-architectural techniques have been proposed, which lead to the design of variety of processors, from simple in-order pipeline processors to recent multi-core processors. The course provides a detailed understanding of various processor microarchitectural designs, which include in-order scalar pipeline design, out-of-order superscalar processor design, and multicore processor design. (from

Lecture 20 - Compiler Optimizations for Exposing ILP

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Lecture 01 - Introduction to Computer Architecture
Instruction Set Architecture (ISA)
Lecture 02 - Quantitative Principles of Computer Design
Lecture 03 - Instruction Set Principles: The Role of ISA, ISA Classification, Memory Addressing
Lecture 04 - Instruction Set Principles: Addressing Modes
Lecture 05 - Instruction Set Principles: Types of Operands and Operations, Encoding an ISA
Memory Hierarchy Design - Cache Memory Hierarchy
Lecture 06 - Cache Memory Hierarchy
Lecture 07 - Cache Memory Hierarchy: The Basics of Cache Memory
Lecture 08 - Cache Memory Hierarchy: Basic Cache Optimizations
Lecture 09 - Cache Memory Hierarchy: Advanced Optimizations
Memory Hierarchy Design - Main Memory Design
Lecture 10 - Main Memory Design: Basics of DRAM based Memory
Lecture 11 - Main Memory Design: DRAM based Memory Controller Design
Lecture 12 - Main Memory Design: DRAM based Memory Controller Design (cont.)
Fundamentals of Pipelining
Lecture 13 - Pipelining Concept and Examples
Lecture 14 - Instruction Pipelining
Lecture 15 - Pipeline Hazards
Lecture 16 - Handling Pipeline Hazards
Lecture 17 - Implementation of MIPS pipeline
Instruction Level Parallelism
Lecture 18 - Scalar Pipeline to Superscalar Pipeline
Lecture 19 - Instruction Dependencies
Lecture 20 - Compiler Optimizations for Exposing ILP
Lecture 21 - Advanced Branch Prediction Techniques: Correlated Branch Predictors
Lecture 22 - Advanced Branch Prediction Techniques: Tournament Branch Predictor
Out-of-Order Execution
Lecture 23 - Superscalar Organization
Lecture 24 - Register Renaming
Lecture 25 - Tomasulo Algorithm
Lecture 26 - Dynamic Execution Core
Thread Level Parallelism - Multicore Processors
Lecture 27 - Multithreading
Lecture 28 - Multicore Processors
Lecture 29 - Cache Coherence
Lecture 30 - Cache Coherence Protocol Design
Lecture 31 - Synchronization
Lecture 32 - Memory Consistency: Sequential Consistency Model
Lecture 33 - Memory Consistency: Total Store Order and Relaxed Consistency Models