Multi-core Computer Architecture: Storage and Interconnects

Multi-core Computer Architecture: Storage and Interconnects. Instructor: Prof. John Jose, Department of Computer Science and Engineering, IIT Guwahati. We are in the era of multi-core systems where even the simplest of handheld devices like a smartphone houses many processors in a single chip. The core counts are ever increasing from 8 to 10 in smart phones to over 100s in supercomputers. This course will introduce the students to the world of multi-core computer architectures. With the unprecedented growth of data science, on-chip storage systems and inter-core communication framework are getting equal attention as that of processors. This course will focus on delivering an in-depth exposure in memory-subsystems and interconnects of Tiled Chip Multi-Core Processors with few introductory sessions on advanced superscalar processors. The course concludes with pointers to current research standings and on-going research directions for motivating the students to explore further. (from

Lecture 16 - Introduction to DRAM System

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Pipelined Instruction Execution Principles
Lecture 01 - Introduction
Lecture 02 - Instruction Execution Principles
Lecture 03 - Introduction to Instruction Pipeline
Lecture 04 - Introduction to Superscalar Pipelines
Lecture 05 - Instruction Pipeline and Performance
Lecture 06 - Instruction Pipeline and Performance (cont.)
Cache Memory Design Concepts
Lecture 07 - Introduction to Cache Memory
Lecture 08 - Block Replacement Techniques and Write Strategy
Lecture 09 - gem5 Simulator: An Overview
Lecture 10 - Cache Memory
Basic Cache Optimizations
Lecture 11 - Basic Cache Optimization Techniques
Lecture 12 - gem5 Simulator: Cache Optimization
Advanced Cache Optimizations
Lecture 13 - Advanced Cache Optimization Techniques
Lecture 14 - Advanced Cache Optimization Techniques (cont.)
Lecture 15 - Cache Memory Optimizations
DRAM Technology
Lecture 16 - Introduction to DRAM System
Lecture 17 - DRAM Controllers and Address Mapping
Lecture 18 - Address Translation Mechanisms
Lecture 19 - Main Memory Concepts
Tiled Chip Multi-core Processors and Network-on-Chip
Lecture 20 - Introduction to Tiled Chip Multi-core Processors
Lecture 21 - Routing Techniques in Network-on-Chip
Lecture 22 - Network-on-Chip Router Micro-Architecture
Lecture 23 - gem5 Simulator - NoC Optimization
Network-on-Chip Architectures
Lecture 24 - Energy Efficient Bufferless NoC Routers
Lecture 25 - Side-buffered Deflection Routers
Lecture 26 - Concepts in Network-on-Chip
QoS for TCMPs at Storage and Interconnect Levels
Lecture 27 - QoS of NoC and Caches in TCMP Systems
Lecture 28 - Emerging Trends in Network on Chips
Lecture 29 - Concepts in TCMP Systems