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Advanced Logic Synthesis

Advanced Logic Synthesis. Instructor: Dhiraj Taneja, Broadcom, Hyderabad. The goal of the course is to study the components of digital design and advanced concepts in synthesis process; to understand the importance of technology, libraries, design constraints, design rules; to understand the usefulness of reports with respect to design on Area, Timing and Power. (from nptel.ac.in)

Lecture 25 - Equivalence Checking/ Formal Verification


Go to the Course Home or watch other lectures:

MOS Transistor
Lecture 01 - MOS Transistor
Lecture 02 - MOS Transistor: Detailed Study
Digital Timing in CMOS
Lecture 03 - Combinational Circuits and Layout
Lecture 04 - Delay
Lecture 05 - Sequential Circuits
Lecture 06 - Logical Effort
Lecture 07 - Circuit Families
Process of Synthesis, Libraries and Technology Mapping
Lecture 08 - Introduction to Synthesis
Lecture 09 - Libraries
Lecture 10 - RTL Coding Synthesis
Lecture 11 - Reading Design in DC
Lecture 12 - Design Environment
Lecture 13 - Design Constraints
Lecture 14 - Compile Flow and Strategies
Lecture 15 - Analysis and Reporting
Advanced Synthesis Flow
Lecture 16 - Advanced Synthesis Techniques
Lecture 17 - Datapath Extraction Guidelines
Lecture 18 - Power - Methodology and Analysis
Timing Analysis
Lecture 19 - Static Timing Analysis - Concepts and Flow
Lecture 20 - Interconnects and Delay Calculation
Lecture 21 - Clock and Exceptions
Lecture 22 - On Chip Variation
Lecture 23 - Introduction to Crosstalk
Lecture 24 - Gaussian/Normal Distribution
Lecture 25 - Equivalence Checking/ Formal Verification